library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


library lib_ExpoRNS;
entity trc_bench is
end trc_bench;
architecture test_TRC of trc_bench is


  component trc_Unit
    generic (
      Z : positive  := 15;              

      --Vecteur de base
      alpha : positive := 8;
      beta1 : positive :=7;
      beta2 : positive := 3;

      --Calcul pour le TRC
      e1 : positive  := 105;  --8 
      e2 : positive  :=120;  --7
      e3 : positive := 112  --3
      );
      port (
        a1 : in  unsigned(Z-1 downto 0);
        a2 : in  unsigned(Z-1 downto 0);
        a3 : in  unsigned(Z-1 downto 0);
        s  : out unsigned(Z-1 downto 0)

        );
  end component;
  signal a1 : unsigned(14 downto 0) ;
  signal a2 : unsigned(14 downto 0) ;
  signal a3 : unsigned(14 downto 0) ;
  signal sortie : unsigned(14 downto 0);
  
begin  -- test_TRC
    trc:trc_Unit port map(a1,a2,a3,sortie);

  process
    constant delay: time :=10 ns;    
  begin


    a1<= to_unsigned(1, 15);
    a2<=to_unsigned(2, 15);
    a3<=to_unsigned(0, 15); 

    wait for delay;

   -- assert false report " FIN DE LA SIMULATION" severity failure;

  end process;    
end test_TRC;
